In the field of display technology, an array of pixels of a liquid crystal display typically includes a plurality of rows of gate lines and a plurality of columns of data lines crossed with each other, wherein driving of the gate lines can be implemented through an attached integrated driving circuit. In recent years, with continuous development of the amorphous silicon thin film manufacturing process, a gate driving circuit can also be integrated on a thin film transistor array substrate so as to form a GOA (Gate driver On Array) for driving the gate lines.
A plurality of shift register units can be adopted to form the GOA to provide a switching signal to a plurality of rows of gate lines of a pixel array, so as to control the plurality of rows of gate lines to be turned on sequentially, and the data lines apply display data signals to pixels in the corresponding rows in the pixel array, so as to form grayscale voltages required to display respective gray scales of an image, and then each frame of the image is displayed.
In an existing gate line driving device, after the shift register unit in a current stage completes its output, in order to reset an output terminal of the shift register unit in the current stage, an output signal from an shift register unit in a next stage is typically taken as a reset signal for the shift register unit in the current stage to control a pull-down transistor, so as to reset the output terminal of the shift register unit in the current stage. However, the transistor that pulls down the output terminal of the shift register unit usually has a large size and a low use efficiency, which is inimical to circuit downsizing and power consumption reducing. Meanwhile, resetting of the shift register unit in a previous stage and triggering of the shift register unit in a next stage are both completed through a signal outputted from an output transistor of the shift register unit in the current stage, thus the output transistor of the shift register unit in the current stage has a large load, which results in a signal output delay. In addition, if the output transistor has a failure, not only a poor signal output would be generated in the gate line corresponding to the current stage, but also an output failure would occur in the gate lines in the previous stage and the next stage.